Expanding Functions when Ida Fails

Posted by Eric | Architecture, Python, Reversing | Tuesday 1 July 2008 10:46 am

Functions all start out with some type of prologue. Powerpc is no different. I was recently taking apart some firmware when I discovered the need to have an IDA Script take care of some function creations. Since the firmware was so large I didn’t really want to continue scrolling down and manually converting the data to code by pressing ‘c’.

In order to have Ida Python create functions automatically you can use two functions.

FindBinary
and
MakeFunction

the concept is to use FindBinary to locate the standard function prologue byte code and from there, create a function using MakeFunction. Using a python while loop you can create a short IdaPython script to expand your disassembly. I ran it on a fairly large piece of firmware and it ended up handling a lot of the disassembly that Ida’s auto analysis failed to complete due to the lack of a true entry point.

When it comes to PowerPC our prologue is going to look something like this

mflr r0 ; Save the link register to r0
stw r0, 4(rsp) ; Save r0 to register commonly used as stack pointer
stwu rsp,-16(rsp) ; Create frame
stw r31, 12(rsp); Save r31

For the particular piece of firmware I was playing with it was not saving the link register. Our prologue began with a stwu instruction. So, we use FindBinary to locate all instances of 0×9421. Although the method is not perfect, on a large scale it’s much easier to automate the creation of functions via IdaPython or IDC and have a few errors, than it is to manually create all the functions.

In terms of a prologue, you are usually left with some type of branching instruction. For most functions it just be a BLR instruction which is “Branch to Link Register”

PPC Notes

Posted by Eric | Architecture, Research | Tuesday 24 June 2008 10:48 am

Been working through PowerPC assembly and Mysql as of Late.

As I was browsing through the book store hanging out with my son I noticed a copy of the database hackers handbook for less than $9.00, Figured I can’t go wrong at that price. I never really had an interest in databases but as I flipped through the book I realized that aside from a general ability to run through SQL commands I didn’t really have a good understanding of database systems. I created a nice syllabus to run through Mysql for the moment. Towards the latter half I’ll actually get into SQL Injections so if you’ve got some decent tuts in your link base drop it!

Anyway, PowerPC assembly is Hot, still a bit vexing since I’m used to Intel. However I see how PPC is much cleaner and more efficient. For those interested I’ve been taking notes as I follow through a syllabus for learning PPC that I created. I modeled it off the Professional Assembly programming book by Wrox publishing (which mind you is an awesome book for the Intel architecture). Right now I’ve only dropped the architecture overview notes, I am working through Moving data around and Stacks. PPC is really interesting when you get to stacks since it doesn’t necessarily have hardware support for one. However, using registers and some instructions you can create a stack and manipulate it. However, there are no formally defined instructions for it such as Intel’s PUSH and POP.

Notes are in Here.

Power Pc Intro

Posted by Eric | Architecture, Research | Sunday 13 January 2008 12:17 am

<meta name="GENERATOR" content="OpenOffice.org 2.0 (Linux)" /><meta name="CREATED" content="20080110;21250500" /><meta name="CHANGED" content="20080112;22152400" /><br /> <style> <!-- @page { size: 8.5in 11in; margin: 0.79in } P { margin-bottom: 0.08in } --> </style> <p style="margin-bottom: 0in">PowerPC runs on a Reduced Instruction set (RISC) and Intel runs on a Complex Instruction set (CISC). RISC is a CPU strategy that focuses on simplified instructions which do less, but may still provide for higher performances if the simplicity can make instructions execute very fast. SPARC, ARM and MIPS also run on a Reduced instruction set. Intel on the other hand, utilizes a complex instruction set which, within each instruction can execute several low level operations such as load from memory, do a math operation and perform a memory store all in one instruction.</p> <p style="margin-bottom: 0in"> <p style="margin-bottom: 0in">The Power PC Architecture has some of the following features.</p> <p style="margin-bottom: 0in"> <p style="margin-bottom: 0in">Separate 32 bit register file for integer and floating point instructions.</p> <ul> <li> <p style="margin-bottom: 0in">The General purpose registers hold source data for integer arithmetic instructions</p> </li> <li> <p style="margin-bottom: 0in">The Floating point registers hold source and target data for floating point arithmetic instructions.</p> </li> </ul> <p style="margin-bottom: 0in"> <p style="margin-bottom: 0in">Instructions for handling data loading and storing between memory and the FPR and GPR’s</p> <p style="margin-bottom: 0in">The ability to perform both single and double precision floating point operations</p> <p style="margin-bottom: 0in">User level instructions for storing, flushing and invalidating data in the on chip caches.</p> <p style="margin-bottom: 0in">Support for both big and little endian addressing modes</p> <p style="margin-bottom: 0in"> <p style="margin-bottom: 0in">The Power PC Architecture is defined in three levels, This layering of the architecture provides flexibility, allowing degress of software compatibility across a wide range of implementations. The three levels of architecture are:</p> <ul> <li> <p style="margin-bottom: 0in">User Instruction set architecture : Which defines the base user level instruction set, user level registers, data types, floating point memory and interrupt model as seen by user programs.</p> </li> <li> <p style="margin-bottom: 0in">Virtual Environment Architecture: which defines additional user level functionality that fall outside typical user level software requirements.</p> </li> <li> <p style="margin-bottom: 0in">Operating environment architecture: Which defines supervisor level resources, which are typically required by an operating system.</p> </li> </ul> <p>For further information on Risc, And CISC:</p> <p>http://en.wikipedia.org/wiki/RISC</p> <p>http://en.wikipedia.org/wiki/Complex_instruction_set_computer</p> <p>http://cse.stanford.edu/class/sophomore-college/projects-00/risc/risccisc/</p> <p style="margin-bottom: 0in"> </div> <div class="feedback"> <a href="http://hamsterswheel.com/techblog/?p=34#respond" title="Comment on Power Pc Intro">Comments (0)</a> </div> </div> </div> <div id="footer"> © Copyright 2009 | <a href="http://hamsterswheel.com/techblog">Phn1x – Hamsterswheel</a> | Theme by <a href="http://clubparexcellancetech.com/">Club Par Excellance</a> | All Rights Reserved | Sponsored by <a href="http://www.voipkit.ca/">VoIP</a> </div> </body> </html>